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| ? integrated circuits group lh 28 f 16 0 s 3 ht - l 10 a fla sh me mor y 16 m ( 2 m b 8 / 1 mb 16 ) (model no.: lh f 16 ka 7 ) spec no.: el 1 2 7 1 11 a issue date: a ugu st 2 9 , 20 0 0 p roduc t s pecific a tions
sharp lhf16ka7 . - - l handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). i *office electronics l instrumentation and measuring equipment l machine tools aaudiovisual equipment *home appliance l communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. -control and safety devices for airplanes, trains, automobiles, and other transportation equipment *mainframe computers l tcaff ic control systems agas leak detectors and automatic cutoff devices *rescue and security equipment @other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. aaerospace equipment l communications equipment for trunk lines l control equipment for the nuclear power industry l medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company. rev.1.9 sharp _- . - lhf16ka7 1 -- contents page page i introduction ...................................................... 3 1.1 product overview.. .............................................. 3 2 principles of operation ................................ 6 2.1 data protection ................................................... 7 3 bus operation.. .................................................. 7 3.1 read ................................................................... 7 3.2 o&put disable .................................................... 7 3.3 standby.. ............................................................. 7 3.4 deep power-down .............................................. 7 3.5 read identifier codes operation.. ....................... 8 3.6 query operation .................................................. 8 3.7 write.. .................................................................. 8 5 design considerations ................................ .3c 5.1 three-line output control ................................ .3c 5.2 sts and block erase, full chip erase, (multi) word/byte write and block lock-bit configuration polling ................................................................ 3c 5.3 power supply decoupling .................................. 3c 5.4 v,, trace on printed circuit boards.. ............... .3c 5.5 vcc, v,,,, rp# transitions.. .............................. .31 5.6 power-up/down protection.. ............................. .31 5.7 power dissipation ............................................. .31 1 command definitions.. ..................................... 8 4.1 read array command ....................................... 11 4.2 read identifier codes command ...................... 11 4.3 read status register command.. ..................... 11 4.4 clear status register command.. ..................... 11 4.5 query command ............................................... 12 4.51 block status register .................................. 12 4.5.2 cfi query identification stang.. ................... 13 4.5.3 system interface.lnformation.. ..................... 13 4.5.4 device geometry definition ......................... 14 4.5.5 scs oem specific extended query table.. 14 4.6 block erase command.. .................................... 15 4.7 full chip erase command ................................ 15 4.8 word/byte write command.. ............................. 16 4.9 multi word/byte write command ...................... 16 4.10 block erase suspend command.. ................... 17 4.11 (multi) word/byte write suspend command ... 17 4.12 set block lock-bit command.. ........................ 18 4.13 clear block lock-bits command.. ................... 18 4.14 sts configuration command ......................... 19 6 electrical specifications.. ........................ .3i 6.1 absolute maximum ratings .............................. .3i 6.2 operating conditions ......................................... 32 6.2.1 capacitance ................................................. 32 6.2.2 ac input/output test conditions.. ............... .3z 6.2.3 dc characteristics ........................................ 34 6.2.4 ac characteristics - read-only operations .3e 6.2.5 ac characteristics - write operations.. ....... .3e 6.2.6 alternative ce#-controlled writes.. ............. .41 6.2.7 reset operations ........................................ .4z 6.2.8 block erase, full chip erase, (multi) word/byte write and block lock-bit configuration performance.. ........................ .44 7 additional information ................................ 4e 7.1 ordering information .......................................... 46 - rev. 1.9 shal?p lhflgka7 2 - lh28f160s3ht-ll oa 1 gm-bit (2mbx8/1 mbxl6) smart 3 flash memory n smart 3 technology n enhanced data protection features - 2.7v or 3.3v vcc - absolute protection with vpp=gnd - 2.7v, 3.3v or sv vpp - flexible block locking i common flash interface (cfi) - erase/write lockout during power transitions - universal & upgradable interface i scalable command set (scs) n extended cycling capability - 100,000 block erase cycles n high speed write performance - 3.2 million block erase cycles/chip - 32 bytes x 2 plane page buffer n low power management - 2.7 @byte write transfer rate - deep power-down mode n high speed read performance - automatic power savings mode - 1 oons(3.3v*o.3v), 120ns(2.7\1-3.6v) decreases icc in static mode i operating temperature n automated write and erase - -40c to +85x - command user interface n enhanced automated suspend options - status register - write suspend to read n industry-standard packaging - block erase suspend to write - 56-lead tsop - block erase suspend to read n etogtm* v nonvolatile flash n high-density symmetrically-blocked technology architecture thirty-two 64k-byte erasable blocks n cmos process - (p-type silicon substrate) i sram-compatible write interface i user-configurable x8 or x16 operation n not designed or rated as radiation hardened sharp?s lh28f160s3ht-lloa flash memory with smart 3 technology is a high-density, low-cost, nonvolatile, *cad/write storage solution for a wide range of applications. its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, slmms and memory :ards. its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the lh28f160s3ht-lloa offers three levels of protection: absolute protection with v,, at ?nd, selective hardware block locking, or flexible software block locking. these alternatives give designers jltimate control of their code security needs. the lh28f160s3ht-lloa is conformed to the flash scalable command set (scs) and the common flash nterface (cfi) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. the lh28f160s3ht-lloa is manufactured on sharp?s 0.35um etox tm* v process technology. it come in ndustry-standard package: the 56-lead tsop ideal for board constrained applications. ?etox is a trademark of intel corporation. rev. 1.9 sharp lhflgka7 3 . - 1 introduction this datasheet contains lh28f160s3ht-ll oa specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1 .l product overview the lh28f160s3ht-ll oa is a high-performance 16m-bit smart 3 flash memory organized as 2mbx80mbxl6. the 2mb of data is arranged in thirty-two 64k-byte blocks which are individually erasable, lockable, and unlockable in-system. the memory map is shown in figure 3. smart 3? technology provides a choice of v,, and v,, combinations, as shown in table 1, to meet system performance and power expectations. 2.7v vc, consumes approximately one-fifth the power of 5v vc,. v,, at 2.7v, 3.3v and 5v eliminates the need for a separate 12v converter, while v,,=5v maximizes erase and write performance. in addition to flexible erase and program voltages, the dedicated v,, pin gives complete data protection when table 1. vcc and vpp voltage combinations offered by smart 3 technology vcc voltage vpp voltage 2.7v 2.7v, 3.3v, 5v 3.3v 3.3v, 5v internal vw and vp, detection circuitry automatically configures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. 4 block erase operation erases one of the device?s %lk-byte blocks typically within 0.41s (3.3v vcc, 5v vp,) independent of other blocks. each block can be independently erased 100,000 times (3.2 million olock erases per device). block erase suspend mode allows system software to suspend block erase to read or write data from any other block. a word/byte write is performed in byte increments typically within 12.95ps (3.3v v,,, 5v vp,). a multi word/byte write has high speed write performance of 2.7@byte (3.3v v,,, 5v vp,). (multi) word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. individual block locking uses a combination of bits and wp#, thirty-two block lock-bits, to lock ant unlock blocks. block lock-bits gate block erase, full chip erase and (multi) word/byte write operations. block lock-bit configuration operations (set block lock-bit and clear block lock-bits commands) sei and cleared block lock-bits. the status register indicates when the wsm?s block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is finished. the sts output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status maskins (interrupt masking for background block erase, fol example). status polling using sts minimizes bott cpu overhead and system power consumption. sts pin can be configured to different states using the configuration command. the sts pin defaults tc ry/by# operation. when low, sts indicates that the wsm is performing a block erase, full chip erase (multi) word/byte write or block lock-bit configuration sts-high z indicates that the wsm is ready for a new command, block erase is suspended and (multi: word/byte write are inactive, (multi) word/byte write are suspended, or the device is in deep power-dowr mode. the other 3 alternate configurations are al pulse mode for use as a system interrupt. the access time is 100ns (tavqv) over the extendec temperature range (-40c to +85?c) and vc, suppi\ voltage range of 3.ov-3.6v. at lower v,, voltage, the access time is 120ns (2.7v-3.6v). the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps m?ode, the typical i,,, current is 3 ma at 3.3v v,c. when either ce,# or ce,#, and rp# pins are at v,, the i,, cmos standby mode is enabled. when the rp# pin is at gnd, deep power-down mode ic enabled which minimizes power consumption and provides write protection during reset. a reset time (tphav) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (tphel) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. the device is available in 56-lead tsop (thin small outline package, 1.2 mm thick). pinout is shown in figure 2. 1 rev. 1.9 sharp lhflgka7 4 cl3 wex oe% rp# wp# nc ke,# nc ./ azo ais al6 a17 al6 vcc a15 al.4 a13 al2 ceo# vpp rp# 41 aio as ae gnd a7 as a5 2 a2 ai comparator i/ + b ii-4 i : 3 4 5 6 ?7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 figure 1. block diagram ----g-l 56 lead tsop standard pinout 14mm x 20mm top view 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 d 23 34 1 24 25 26 33 i 32 i 31 ) 30 29 wp# we# oe# sts dq15 z:, dq6 gnd dq13 dq5 dq12 dq4 vcc gnd dqll dq3 dqlo dqz vcc dqp dq; dqe dqo a0 byte# nc nc figure 2. tsop 56-lead pinout (normal bend) rev. 1.9 sharp lhf16ka7 5 _ - - i *o-*20 x&)-dc+! i ceo% ce,# rp# oe# we# sts wp# byte# ?pp ?cc gnd nc i type input input/ 3utput t input input input input open drain output twput lnput supply supply supply name and function address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. ao: byte select address. not used in x16 mode(can be floated). ai-ak column address. selects 1 of 16 bit lines. a+ai5: row address. selects 1 of 2048 word lines. a164420 : block address. data input/outputs: dqo-dq,:lnputs data and commands during cui write cycles; outputs data during memory array, status register, query, and identifier code read cycles. data pins float to high- impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dqs-dq15:lnputs data during cui write cycles in x16 mode; outputs data during memory array read cycles in xl 6 mode; not used for status register, query and identifier code read mode. data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x8 mode(byte#=v,, ). data is internally latched during a write cycle. chip enable: activates the device?s control logic, input buffers decoders, and sense amplifiers. either ce,# or ce,# v,, deselects the device and reduces power consumption to standby levels. both ce,-# and ce,# must be v,, to select the devices. reset/deep power-down: puts the device in deep power-down mode and resets internal automation. rp# v,, enables normal operation. when driven \jil, rp# inhibits write operations which provides data protection during power transitions. exit from deep power-down sets the device to read array mode. output enable: gates the device?s outputs during a read cycle. write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. sts (ry/by#): indicates the status of the internal wsm. when configured in level mode (default mode), it acts as a ry/by# pin. when low, the wsm is performing an internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit configuration). sts high z indicates that the wsm is ready for new commands, block erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or the device is in deep power-down mode. for alternate configurations of the status pin, see the configuration command. write protect: master control for block locking. when v,,, locked blocks can not be erased and programmed, and block lock-bits can not be set and reset. byte enable: byte# v,, places device in x8 mode. all data is then input or output on dqo-,, and dqse15 float. byte# v,, places the device in x16 mode , and turns off the a, input buffer. block erase, full chip erase, (multi) word/byte write, block lock- bit configuration power supply: for erasing array blocks, writing bytes or configuring block lock-bits. with v+v+~,k, memory contents cannot be altered. block erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid vpp (see dc characteristics) produce spurious results and should not be attempted. device power supply: internal detection configures the device for 2.7? or 3.3? operation. to switch from one voltage to another, ramp v,, down to gnd and then ramp v,, to the new voltage. do not float any power pins. with v,,iv,,,, all write attempts to the flash memory are inhibited. device operations at invalid v,, voltage (see dc characteristics) produce spurious results and should not be attempted. ground: do not float any ground pins. no connect: lead is not internal connected; it may be driven or floated. table 2. pin descriptions rev. 1.9 sharp r lhflgka7 6 . - .i 1 2 principles of operation the lh28f160s3ht-ll oa flash memory includes an on-chip wsm to manage block erase, full chip erase, (multi) word/byte write and block lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status :egister, query structure and identifier codes can be accessed through the cui independent of the v,, voltage. high voltage on vpp enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. all functions associated with altering memory contents-block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, status, query and identifier codes-are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase, full chip erase, (multi) word/byte write and block lock- bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latch during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, outputs query structure or outputs status register data. interface software that initiates and polls progress of block erase, full chip erase, (multi) word/byte write and block lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read or write data from any other block. write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location. 64k-byte block 3?1 1affff 1 aoow isffff 1soockl 1sffff laow0 17ffff 17omo igffff 160000 15ffff 15oom) 14ffff 14oooo 13ffff ,-mm ipffff 4~cyyi 1lffff 11ocw 1offff lcmoa offfff ofoooo oeffff oeoooo oijffff odoooo ocffff ocoooo obffff 64k-byte block 26 64k-byte block 25 64k-byte block 24 64k-byte block 23 64k-byte block 22 64k-byte block 21 64k-byte block 20 64k-byte block 19 64k-byte block ?81 64k-byte block 17 64k-byte block 16 64k-byte block 15 64k-byte block 14 64k-byte block 13 64k-byte block 12 64k-byte block 11 oaffff oaowo osffff osowo 08ffff okcoo 07ffff 07woo ogffff 060000 obffff ne-n 04ffff 04owo oiffff 03ocm ozffff ozwoo 01 ffff 01wo0 ooffff 64k-byte block 10 64k-byte block 9 64k-byte block 8 64k-byte block 7 64k-byte block 6 64k-byte block 5 64k-byte block 4 3 64k-byte block 2 64k-byte block 64k-byte block 1 64k-bvte block 0 figure 3. memory map l rev. 1.9 sharp lhflgka7 7 - 2.1 data protection depending on the application, the system designer may choose to make the v,, power supply switchable (available only when block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are required) or hardwired to vpph1,2/3. the device accommodates either design practice and encourages optimization of the processor-memory interface. when vpp~vpplkt memory contents cannot be altered. the cui, with multi-step block erase, full chip erase, (multi) word/byte write and block lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage,is applied to v,,. all write functions are disabled when vcc is below the write lockout voltage v,,, or when rp# is at v,,. the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and (multi) word/byte write operations. 3 bus operation the local cpu reads and writes flash memory in- system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes, query structure,?or status register independent of the v,, voltage. rp# must be at vi,. the first task is to write the appropriate read mode command (read array, read identifier codes, query or read status register) to the cui. upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. five control pins dictate the data flow in and out of the component: ce# (ce,#, ce,#), oe#, we#, rp# and wp#. ce,#, ce,# and oe# must be driven active to obtain data at the outputs. ce,#, ce,# is the device selection control, and when active enables the selected memory device. oe# is the data output (dc&-dq,,) control and when active drives the selected memory data onto the i/o bus. we# and rp# must be at v,,. figure 17, 18 illustrates a read cycle. 3.2 output disable -l with oe# at a logic-high level (vi,), the devict outputs are disabled. output pins do,-dq,, an placed in a high-impedance state. 3.3 standby either ce,# or ce,# at a logic-high level (v,,) place: the device in standby mode which substantiall! reduces device power consumption. dqo-dq,, outputs are placed in a high-impedance statt independent of oe#. if deselected during bloc1 erase, full chip erase, (multi) word/byte write ant block lock-bit configuration, the device continue: functioning, and consuming active power until the operation completes. 3.4 deep power-down rp# at v,, initiates the deep power-down mode. in read modes, rp#-low deselects the memory places output drivers in a high-impedance state ant turns off all internal circuits. rp# must be held low fol a minimum of 100 ns. time t,,crv is required after return from power-down until initial memory access outputs are valid. after this wakeup interval, norma operation is restored. the cui is reset to read arra) mode and status register is set to 80h. during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration modes, rp#-low will abort the operation. sts remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time tphwl is required after rp# goes to logic-high (v,,) before another command can be written. as with any automated device, it is important tc assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. rev. 1 .q lhflgka7 8 _ - i -- 3.5 read identifier codes operation 3.6 query operation the read identifier codes operation outputs the manufacturer code, device code, block status codes for each block (see figure 4). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block status codes identify locked or unlocked block setting and erase completed or erase uncompleted condition. the query operation outputs the query structure. query database is stored in the 48byte rom. query structure allows system software to gain critical information for controlling the flash component. query structure are always presented on the lowest- order data output (dqc-dq,) only. 3.7 write 1fffff :.. : '. : :. . . .,. .: ,;.' > . . . . ..a. 1;; ,, . . . ,., . . '. .' j.: r&&&&, .,:, ': .:' .: l !", ,: :. .. future ~+irnentatt~n '. :'.. ;. ;. ,fm; .. :. ,k)oo5 iilr-' l_l..d+ - -----------_-------1---- if0004 block 31 status code ,fooo3 t ---,-. ~ _____ --; ____ t-------y---i jgxwv~d for ;. tfutye h$e.merrtiian ,foooo :,. ., :?i: : b&;k31 ieffff;:. :' . ; : ':,,.. :. : : m.. w. :. : . . '(~ioiks2thi~gl-l~) ; 02oooo; ,+ ..: ,, '. ', : .,. :. olffff ', " : ..,i. ; ,:" "') o,o(y& (i ? y., l---l-l---l-~--l?l-l----rll---lll-l--------- 01ooo5 ./? 010004 block 1 status code 010003- ___________ --- ______ ---__---------- . . .. i&e&ed~for ,: : .; :.. .: .f;uture:?tmplemen~tiqn .. 01~ 1. .,: .? ?., block? ooffff ;. 1. resewed far future implementation ooooo6 . . ___- -- ____ -- ____ --------_------ ------ coo005 ooocq4 block 0 status code _____-_____-_______------------------ ooani3 oomo2 device code ____________________----------------- oooqo1 manufacturer code block ( figure 4. device identifier code memory map writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when vcc=vcc1,2 and vpp=vppht/2/3, the cui additionally controls block erase, full chip erase, (multi) wordlbyte write and block lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the word/byte write command requires the command and address of the location to be written. set block lock-bit command requires the command and block address within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 19 and 20 illustrate we# and ce#-controlled write operations. 4 command definitions when the v,, voltage i v,,,,, read operations from the status register, identifier codes, query, or blocks are enabled. placing v,,,,,us on v,, enables successful block erase, full chip erase, (multi) word/byte write and block lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands. rev. 1.9 sharp lhflgka7 9 _- = 1 address 1 vpp 1 dqnm15 1 sts table 3. bus operations(byte#=v,uj notes rp# ce?# ce,# oe# we# 1,2,3,9 v,w v,, v,, v,, v,h x x d&r x 3 v,h v,, v,, v,w v,h x x high z x v,,, 11 1 v mode read output disable jeep power-down lead identifier lodes query 4 v,, x x x x x x high z high z 9 vi, %l %l 4, 4, see figure 4 x note 5 high z 9 vlh vi, 4, vi, vlh see table x 7-11 note 6 high z write i i i i i i 1 3,7&w 1 ?.?,h 1 vii 1 vii 1 vi?i 1 vii i x 1 x 1 din i x deep power-down read identifier codes vi, v,w 4 vi, x x x x x x high z high z 9 ?1, vll vi, yl ?1, see figure 4 x note 5 high z query write notes: 9 ?1, 3,7,8,9 vi,, vi, vii vi, vii vi, vlh seetable x 7-11 note 6 high z v,h vii x x din x 1. refer to dc characteristics. when v&f,,,,, memory contents can be read, but not altered. 2. x can be v,, or vrh for control pins and addresses, and vp,,, or vpr+rt/2/s for v,,. see dc characteristics for bplk and vpph1/~3 voitagese 3. sts is v,, (if configured to ry/by# mode) when the wsm is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms. it is floated during when the wsm is not busy, in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or deep power;down mode. . 4. rp# at gn&o.2v ensures the lowest deep power-down current. 5. see section 4.2 for read identifier code data. 6. see section 4.5 for query data. 7. command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are reliably executed when vpp=vpph1/2/3 and vcc=vcc1~2. 8. refer to table 4 for valid d,, during a write operation. 9. don?t use the timing both oe# and we# are vi,. , rev. 1.9 sharp . - lhflgka7 10 i .i i command read array/reset table 4. command definitions(l?) bus cycles notes first bus cycle second bus cycle req?d oper(?) 1 add&*) 1 data13) ope#) 1 addr(*) 1 data13) 1 write ( x 1 ffh 22 4 write x 90h read ia ?d ii 22 write x 98h read qa c 2 write x 70h read x t _ . .._- write x 2 5 write ba 2 write x 2 55 write wa 4lternate word/byte write setupwrite multi word/byte write setup/confirm block erase and (multi) word/byte write suspend confirm and block erase and (multi) word/byte write resume block lock-bit set setup/confirm block lock-bit reset setup/confirm sts configuration level-mode for erase and write (ry/by# mode) sts configuration pulse-mode for erase sts configuration pulse-mode for write sts configuration pulse-mode for erase and write 2 596 write wa 10h write wa wd 24 9 write wa e8h write wa n-l 1 5 write x boh 1 5 write x doh 2 7 write ba 60h write ba olh 2 8 write x 60h write x doh 2 write x b8h write x ooh 2 write x b8h write x olh 2 write x b8h write x 02h 2 write x b8h write x 03h notes: 1. bus operations are defined in table 3 and table 3.1. 2. x=any valid address within the device. ia=ldentifiep code address: see figure 4. qa=quety offset address. ba=address within the. block being erased or locked. wa=address of memory location to be written. 3. srd=data read from status register. see table 14 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id=data read from identifier codes. qd=data read from query database. 4. following the read identifier codes command, read operations access manufacturer, device and block status codes. see section 4.2 for read identifier code data. 5. if the block is locked, wp# must be at vi, to enable block erase or (multi) word/byte write operations. attempts to issue a block erase or (multi) word/byte write to a locked block while rp# is vi,. 6. either 40h or 10h are recognized by the wsm as the byte write setup. 7. a block lock-bit can be set while wp# is vi,. 8. wp# must be at vi, to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. 9. following the third bus cycle, inputs the write address and write data of ?n? times. finally, input the confirm command ?doh?. 10. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 1.9 shari= lhf16ka7 11 . - -- 4.1 read array command 4.3 read status register command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend and (multi) word/byte write suspend command. the read array command functions independently of the vp,, voltage and rp# must be vi,* 4.2 f&ad identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 4 retrieve the manufacturer, device, block lock configuration and block erase status (see table 5 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v,, voltage and rp# must be v,,. following the read identifier codes command, the following information can be read: table 5. identifier codes code address manufacture code 00000 00001 ./ device code 00002 00003 data bo block status code *block is unlocked l block is locked x0004(? ) x0005(?) ~ dc&,=0 dqc= 1 *last erase operation completed successfully 1 / dq,=o 1 @last erase operation did not completed successfully oreserved for future use note: dq,=l dqyw7 the status register may be read to determine when i block erase, full chip erase, (multi) word/byte write oi block lock-bit configuration is complete and whethei the operation completed successfully(see table 14) it may be read at any time by writing the read statu: register command. after writing this command, al subsequent read operations output data from the status register until another valid command is written the status register contents are latched on the fallins edge of oe# or ce#(either ce,# or ce,#) whichever occurs. oe# or ce#(either ce,# or ce,#: must toggle to ?jr, before further reads to update the status register latch. the read status register command functions independently of the v,, voltage rp# must be vi,. the extended status register may be read tc determine multi word/byte write availability(see table 14.1). the extended status register may be read a any time by writing the multi word/byte write command. after writing this command, all subsequen read operations output data from the extended statuz register, until another valid command is written. mult word/byte write command must be re-issued tc update the extended status register latch. 4.4 clear status register command status register bits sr.5, sr.4, sr.3 and sr.l are set to ?1?s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 14). by allowins system software to reset these bits, severa operations (such as cumulatively erasing or lockinc multiple blocks or writing several bytes in sequence: may be performed. the status register may be pollee to determine if an error occurs during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v,, voltage. rp# must be vi,. this command is not functional during block erase, ful chip erase, (multi) word/byte write block lock-bii configuration, block erase suspend or (multi: word/byte write suspend modes. 1. x selects the specific block status code to be read. see figure 4 for the device identifier code memory map. rev. 1.9 sharp . - lhflgka7 12 -- 1.5 query command =luery database can be read by writing query :ommand (98h). following the command write, read ycle from address shown in table 7-l 1 retrieve the xitical information to write, erase and otherwise :ontrol the flash component. a, of query offset address is ignored when x8 mode (byte#=v,l). table 6. example of query structure ( mode off set address ou dq%8 a,, a,, a,, a,, a,, a, 1 , 0 , 0 , 0 (0 , 0 (20h) high z x8 mode 1 , 0 , 0 , 0 , 0 , 1 (21h) high z 1, o,o,o,l ,0(22h) highz 1 , 0 , 0 , 0 , 1 , 1 (23h) high z a,, a,, a,, a,, a, ;luery data are always presented on the low-byte jata output (dc&-d&). in x16 mode, high-byte ;dqs-dq,s) outputs ooh. the bytes not assigned to any information or reserved for future use are set to ?0?. this command functions independently of the jpp voltage. rp# must be v,,. x16mode 1 ,o,o,o,o (10h) ooh l,o,o,o,l (11h) ooh but dqm-, "q" "q" ?r? ?r? ?q? ?r? 1.5.1 block status register this field provides lock configuration and erase status for the specified block. these informations are only available nhen device is ready (sr.7=1). if block erase or full chip erase operation is finished irregulary, block erase status lit will be set to ?1?. if bit 1 is ?l?, this block is invalid. offset (word address) (ba+2)h v? uote: table 7. query block status register length description olh block status register bit0 block lock configuration o=block is unlocked 1 =block is locked bit1 block erase status o=last erase operation completed successfully 1 =last erase operation not completed successfully t&2-7 reserved for future use i. ba=the beginning of a block address. rev. 1.9 sharp lhflgka7 13 _ - -- is.2 cfi query identification string ?he identification string provides verification that the component supports the common flash interface specification. additionally, it indicates which version of the spec and which vendor-specified command set(s) is(are) upported. table 8. cfi query identification string offset (word address) loh,l lh,12h 13h,14h 15h.16h 17h,18h i lsh,lah length description 03h query unique ascii string ?qry? 51 h,52h,59h 02h primary vendor command set and control interface id code 01 h,ooh (scs id code) 02h address for primary algorithm extended query table 31 h,ooh (scs extended query table offset) 02h alternate vendor command set and control interface id code ooooh (ooooh means that no alternate exists) 02h address for alternate algorithm extended query table 1 ooooh (ooooh means that no alternate exists) 1.53 system interface information the following device information can be useful in optimizing system interface software. table 9. system information string offset (word address) length description 1bh olh voc logic supply minimum write/erase voltage 27h (2.7v) 1ch olh v,, logic supply maximum write/erase voltage 55h (5.5v) 1dh olh v,, programming supply minimum.write/erase voltage 27h (2.7v) 1eh olh ./? up,, programming supply maximum write/erase voltage 55h (5.5v) 1fh .olh typical timeout per single byte/word write i03h (23=8us) 20h 1 01 h 1 typical timeout for maximum size buffer write (32 bytes) 06h (26=64us) 21h olh typical timeout per individual block erase oah (oah=lo 21=1024ms) 22h olh typical timeout for full chip erase ofh (ofh=15, 215=32768ms) 23h olh maximum timeout per single byte/word write, 2n times of typical. i04h (24=1 6, 8usxl6=128us) 24h 1 01 h 1 maximum timeout maximum size buffer write, 2n times of typical. 04h (24=1 6, 64usxl6=1024us) 25h olh maximum timeout per individual block erase, 2n times of typical. 04h (24=1 6,1024msxl6=16384ms) 26h olh maximum timeout for full chip erase, 2n times of typical. i04h (24=1 6,32768msxl6=524288ms) _ rev. 1.9 shari= _ - / .i 1.5.4 device geometry definition lhflgka7 14 rhis field provides critical details of the flash device geometry. offset (word address) 27h 28h,29h 2ah,2bh 2ch 2dh,2eh \ 2fh,30h table 10. device geometry definition length description olh device size 15h (15h=21,221=20971 52=2m bytes) 02h flash device interface description 02h,ooh (x8/x16 supports x8 and xl 6 via byte#) 02h maximum number of bytes in multi word/byte write 05h,ooh (2s=32 bytes ) 01h number of erase block regions within device 01 h (symmetrically blocked) 02h the number of erase blocks 1 fh,ooh (1 fh=31 ==> 31+1=32 blocks) 02h the number of ?256 bytes? cluster in a erase block , ooh,olh (olooh=256 ==>256 bytes x 256= 64k bytes in a erase block) 1.5.5 scs oem specific extended query table zertain flash features and commands may be optional in a vendor-specific algorithm specification. the optional rendor-specific query table(s) may be used to specify this and other types of information. these structures are defined solely by the flash vendor(s). offset (word address) 31 h,32h,33h 38h,39h ? 3ah 3bh,3ch 3dh 3eh 3fh tat length 03h olh 31 h (1) major version number , ascii olh 30h (0) minor version number, ascii 04h ofh,ooh,ooh,ooh olh 02h olh olh reserved e 11. scs oem specific extended query table description pri 50h,52h,49h optional command support bito=l : chip erase supported bit1 =l : suspend erase supported bit2=1 : suspend write supported bit3=1 : lock/unlock supported bit4=0 : queued erase not supported bit531 =o : reserved for-future use olh supported functions after suspend bito=l : write supported after erase suspend bit1 -7=o : reserved for future use 03h,ooh block status register mask bito=l : block status register lock bit [bsr.o] active bitl=l : block status register valid bit [bsr.l] active bit2-15=0 : reserved for future use v,, logic supply optimum write/erase voltage(highest performance) 50h@.ov) vpp programming supply optimum write/erase voltage(highest performance) 56i-l(5.ov) deserved for future versions of the scs specification rev. 1.9 . - lhflgka7 15 4.6 block erase command block erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the sts pin or status register bit sr.7. when t$e block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to ?1 ?i. also, reliable block erasure can only occur when vcc=vcc1,2 and vpp=vpph,,2/3. in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v,, sharp _ - lhf16ka7 18 .- - 4.12 set block lock-bit command a flexible block locking and unlocking scheme is enabled via block lock-bits. the block lock-bits gate program and erase operations with wp#=v,,, individual block lock-bits can be set using the set block lock-bit command. see table 13 for a summary of hardware and software write protection options. set block lock-bit is executed by a two-cycle command sequence. the set block lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked). the wsm then controls the set block lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see figure 12). the cpu can detect the completion of the set block lock-bit event by analyzing the sts pin output or status register bit sr.7. when the set block lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally set. an invalid set block lock-bit command will result in status register bits sr.4 and sr.5 being set -to ?1?. also, reliable operations occur only when vcc=vcc1,2 and vpp=vpph,,2,s. in the absence of this high voltage, block lock-bit contents are protected against alteration. 4 successful set block ?lock-bit operation requires rnp#=v,,. if it is attempted with wp#=v,l, sr.l and sr.4 will be set to ?1? and the operation will fail. set yock lock-bit operations with wp# .: . - lhflgka7 20 - table 14. status register definition wsms 1 bess 1 ecblbs 1 wsblbs 1 vpps 1 wss dps r 7 6 5 4 3 2 1 0 notes: sr.7 = write state machine status 1 = ready check sts or sr.7 to determine block erase, full chip 0 = busy erase, (multi) word/byte write or block lock-bit configuration completion. sr.6 = block erase suspend status sr.6-0 are invalid while sr.7=?0?. 1 = block erase suspended 0 = block erase in progress/completed if both sr.5 and sr.4 are ?1 ?s after a block erase, full chip erase, (multi) word/byte write, block lock-bit sr.5 = erase and clear block lock-bits configuration or sts configuration attempt, an improper status command sequence was entered. 1 = error in erase or clear bloc1 lock-bits 0 =isuccessful erase or clear block lock-bits sr.3 does not provide a continuous indication of v,, level. the wsm interrogates and indicates the v,, level sr.4 = write and set block lock-bit status only after block erase, full chip erase, (multi) word/byte 1 = error in write or set block lock-bit write or block lock-bit configuration command 0 = successful write or set block lock-bit sequences. sr.3 is not guaranteed to reports accurate feedback only when v,,#v,,,,,z.s. sr.3 = v,, status 1 = v,, low detect, operation abort sr.l does not provide a continuous indication of block o=v,,ok lock-bit values. the wsm interrogates block lock-bit, and wp# only after block erase, full chip erase, (multi) sr.2 = write suspend status word/byte write or block lock-bit configuration command 1 = write suspended sequences. it informs the system, depending on the 0 = write in progress/completed attempted operation, if the block lock-bit is set and/or sr.1 = device protect status wp# is not v,,. reading the block lock configuration codes after writing the read identifier codes command 1 = block lock-bit and/or wp# lock detected, indicates block lock-bit status. operation abort 0 = unlock sr.0 is reserved for future use and should be masked sr.0 = reserved for future?enhancements out when polling the status register. table 14.1. extended status register definition sms r r r r r r r 7 6 5 4 3 2 1 0 not&: xsr.7 = state machine status 1 = multi word/byte write available after issue a multi word/byte write command: xsr.7 0 = multi word/byte write not available indicates that a next multi word/byte write command is available. xsr.g-o=reserved for future enhancements xsr.g-0 is reserved for future use and should be masked out when polling the extended status register. 1 1 rev. 1.9 shari= <~ . - lhflgka7 21 i start 24 write 70h block address fullstalusc~eckprocedure read status register data(sae above) device protect ertvr block erase error block erase successful read stata data-7ol-l register addr=x data-doh adds-within block to be erased i read status register data repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after tie last operation to place dwico in mad array mode. standby check sr.3 l-vpp enor detect chedt sr.1 i-device protect detect wp#-vil,bkxk lock-bit is set only required for systems implemenbng lock-bit con~@uration check sr.4.5 both l=command sequence error standby check sr.5 l=block erase error srs.sr.4.sr.3 and sr. 1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected. clear the status register before attempting retry or other error recovery. figure 5. automated block erase flowchart rev. 1.9 shari= l- c start 1 f r i full status check if desired fiju status check procedure command sequence error .- _ - lhflgka7 22 . i bus opwlo? command comments wlite read standby read status register data7oh add-x status register data chedt sr.7 l.wsm ready oiwsm busy write write read standby full chip erase sbjp full chip ease confin data=3oh addr-x data-doh ad&x status regtster data check sr.7 l=wsm ready oiwsm busy full stams check can be done after each full chip erase. write ffh after tie last operation to place device in read army mode. bus opedfo? standby standby standby- command commenb check sr.3 l=vpp enor detect check sr.4,5 both l=ccmmand sequence error check sr.5 l=full chip erase error srs,sr.4,sr.3 and sr.l am only dewed by the clear status register command in cases whew multiple blocks are erased before full status is chedmd. if error is detected, clear the status register before attempting retry or other error recovery. figure 6. automated full chip erase flowchart rev. 1.9 shari= _ - lhf16ka7 23 25 write 70h write 40h or 10h. address complete full status check procedure read status r@ster data(see above) dewce protect etmr word/byte write successful read c standby repeat for subsequent w-or&byte writes. comments data-70h addrex stabs register data check sr.7 1 .wsm ready o-wsm busy dataydoh or 10h add-location to be written datedata to 5a written addhlocatfon to se wtitton status register data check sr.7 1 -wsm ready o-wsm busy sr full status check can be done after each wordlbyte wtite, or after a sequence of wodyte writes. white ffh after the last word/byte write operation to place device in read array mode. i standby check sr.1 l-device protect detect wpb-v~@xk lock-bit is set only required for systems implementing lock-bit configuration standby check sr.4 l-data write error sr.4.sr.3 and sr.1 are only cleared by the clear status register command in casw where multiple locations are written before full stahls is checked. f error is detected. clear the status register before attempbng retry or other error recovery. figure 7. automated word/byte write flowchart rev. 1.9 shari= lhf16ka7 read extend status register start address device address read status bus operation command comments write s-p date=ebh ~~16 wordlbyte wlite add&tart address read standby extmded status register data check xsr.7 1-multi word/byte write ready 01multl word/byte write busy write (note0 writ9 (note2.3) wnte (note4.5) write data-word or byte count (n)-1 add&tart address data-buffer data addr=start address data-buffer data addrpdewce address deta=doh addr=x read status register data standby check sr.7 1 =wsm ready o=wsm busy 1, byte or word count values on dt& am loaded into the count register. 2. write buffer contents will be programmed at the start address. 3. align tie start address on a write buffer boundary for maximum programming performance. 4.the device aboris the multi word/byte write command if the current address is outside of the original block address. 5.the status register indicates a? ?improper command sequence if the multi word/byte command is aborted. follow this with a clear status rqster command. sr full status check can be done after each multi wordlbyte write, or after a sequence of multi wordmyie writes. write ffh alter the last multi wordmyte write operation to place device in mad army mode. figure 8. automated multi word/byte write flowchart rev. 1.9 shari= lhf16ka7 full status check procedure for multi word/byte write operation device protect error i bus opwriion command comments standby check sr.3 l=vpp error detect standby check sri l-device pmtecf detect wpbv@bck m-bit is set only required for systems implementing lock-bit configuration standby check sr.4,5 both l-command sequence error standby check sr.4 l-data write error srs,sr.4.sr.3 and sr.l am only deamd by the clear status register command in cases where multiple locations are written before full status is checked. ?f error is detected, clear the status register before attempting retry or other error recovery. figure 9. full status check procedure for automated multi word/byte write rev. 1.9 sharp i road status register :-- sr.75 0 1 + (multi) wordbyte write loop commnd er;ue suspmd i comments df&psoh add-x status register data addhx .- . - lhf16ka7 26 . a- m standby check sr.7 i -wsm ready ocwsm busy standby chock sr.6 l&lock erase suspended o-stock erase completed wlib elbe datasdoh resume addr-x figure 10. block erase suspend/resume flowchart rev. 1.9 sharp w sr.7= 0 1 done no c-l reading yes ella opf&iofl command comments write read (multt) wordleyte write d&&oh suspend add-x status register data addr=x standby standby check sr.7 i-wsm ready o-wsm eury chack sr.2 l-(multi) woweyte write suspmd6d o-(muhi) wordlsyta write cmplatad write read array datawffh addr-x read read anay locations other than that being written. wtite (muic) word/byte write data=doh resume addr-x _ - lhflgka7 27 i figure 11. (multi) word/byte write suspend/resume flowchart rev. 1.9 sharp lhflgka7 check if desired full status check procedure command comments set block data-01 h. write lock-bit confirm addr-block address i i 1 read status register data i check sr.7 standby 1 -wsm ready oawsm busy repeat for subsequent block lock-bit set operations. full status check can be done after each mock lock-bit set operation or after a sequence of block lock-bit set operations. write ffh after the last block lock-bit set operation to place device in read array mode. command comments standby check sr.3 lnvpp error detect standby checksr.1 l-device protect detect wp#=v,l standby check sr.4 standby l-set block lock-sit error i i sr.s,sr.4,sr.3 and sr.l am only deared by the clear status register command in cases where multiple block lock-bits are set before full statlls ls checked. if error is detected. clear the status register before attempting retry or other error recovery. figure 12. set block lock-bit flowchart rev. 1.9 sharp .- . - lhf16ka7 u 0 sr.7- 4 1 chedc if desired full status check procedure read status register data(s-se above) command comments wit0 ffh after tie clear block lock-bits operation to hce device in mad array mode. standby check sr.4.5 both l=command sequence ermr standby check sr.5 l=clear block lock-bits error i sr.s.sr.4.sr.3 and sr. 1 are only deamd by the clear status register command. if error is det+d. clear the status register before attempting retry or other wmr recovery. figure 13. clear block lock-bits flowchart rev. 1.9 lhf16ka7 30 -- 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to xcommodate multiple memory connections. three- jne control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read#icontrol line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes juring system power transitions. powergood should also toggle during system reset. 5.2 sts and block erase, full chip erase, (multi) word/byte write and block lock-bit confjguration polling sts is an open drain output that should be connected to v,, y b a pullup resistor to provide a hardware method of detecting block erase, full chip 3rase, (multi) -word/byte write and block lock-bit configuration completion. in default mode, it transitions low after block erase,, full chip erase, [multi) word/bfie write or block lock-bit configuration commands and returns tp v,, when the wsm has finished executing the internal algorithm. for alternate sts pin configurations, see the configuration command. sts, in default mode, is also high z when the device is in block erase suspend (with (multi) word/byte write inactive), (multi) word/byte write suspend or deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a o.lpf ceramic capacitor connected between its vcc and gnd and between its v,, and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7l.1f electrolytic capacitor should be placed at the array?s power supply connection between vc, and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 vpp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v,, power supply trace. the v,, pin supplies the memory cell current for block erase, full chip erase, (multi) word/byte write and block lock-bit configuration. use similar trace widths and layout considerations given to the v,c power bus. adequate v,, supply traces and decoupling will decrease v,, voltage spikes and overshoots. sts can be connected to an interrupt input of the system cpu or controller. it is active at all times. rev. 1.9 si-iarp _ - lhflgka7 31 .- - 5.5 vcc, vpp, rp# transitions powers-up first. internal circuitry resets the cui tc read array mode at power-up. block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if vp, falls outside of a valid vpph1,2/3 range, vcc falls outside of a valid vccl,s range, or rp#=vil. if v,, error is detected, status register bit sr.3 is set to ?1? along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v,, during block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, sts(if set to ry/by# mode) will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restore& device power-off or rp# transitions to v,, clear the status register. the cui latches commands issued by system software and is not altered by vpp or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power-down or after vcc transitions below vlko. after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration, even after v,, transitions down to vpplk, the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against accidental blqck and full chip , erasure, (multi) word/byte writihg or block lock-bit configuration during power transitions. upon. power-up, the device is indifferent as to which power supply (v,, or vco) a system designer must guard against spuriou: writes for vcc voltages above vlko when v,, i: active. since both we# and ce# must be low for 2 command write, driving either to v,, will inhibit writes the cul?s two-step command sequence architecture provides added level of protection against datz alteration. in-system block lock and unlock capability prevents inadvertent data alteration. the device is disablec while rp#=v,, regardless of its control inputs state. 5.7 power dissipation when designing portable systems, designers musi consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatility increases usable battery life because data is retained when system power is removed. in addition, deep power-down mode ensures extremely low power consumption even when system power is applied. for example, portable computing products and other power sensitive applications thai use an array of devices for solid-state storage can consume negligible power by lowering rp# to v,, standby or sleep modes. if access is again needed, the devices can be read following the t,,qv and tphwl wake-up cycles required after rp# is first raised to v,,. see ac characteristics- read only and write operations and figures 17, 18, 19, 20 for more information. rev. 1.9 sharf= . - lhflgka7 -- - 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, erase, write and block lock-bit configuration . . . ..-40c to +85?c(1) temperature under bias . . . . . . . . . . . . . . . -40c to +85?c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125?c voltage on any pin (except vcc, v,,) . . . . . . . . . . . . . . . -0sv to v,o+0.5v(2) vcc suply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +7.ov(2) v,, update voltage during erase, write and block lock-bit configuration . . . . ..-0.2v to +7.0vt2) output short circuit current . . . . . . . . . . . . . . . . . . . . . . . . 1 00mat3) *warning: stressing the device beyond the ?absolute maximum ratings? may cause permanen damage. these are stress ratings only. operatior beyond the ?operating conditions? is nc recommended and extended exposure beyond the ?operating conditions? may affect device reliability. notes: 1. operating temperature is for extender temperature product defined by this specification. 2. all specified voltages are with respect to gnd minimum dc voltage is -0.5v on input/output pin: and -0.2v on vcc and v,, pins. durin! transitions, this level may undershoot to -2.ov fo periods <20ns. maximum dc voltage or input/output pins and vcc is vc.+o5v which during transitions, may overshoot to vcc+2.0v fo periods <20ns. 3. output shorted for no more than one second. nc more than one output shorted at a time. 6.2 operating conditions temperature and vcc oderating conditions symbol parameter min. max. unit test condition ta operating temperature -40 +85 ?c ambient temperature vc-., vcc supply voltage (2.7v-3.6v) 2.7 3.6 v vccy vcr. supply voltage (3.3vio.3v) 3.0 3.6 v 6.2.1 capacitance(?) .i? symbol parameter c,n input capacitance c(y i-j- output capacitance note: 1. sampled, not 100% tested. t,=+25?c, f=l mhz typ. max. 7 10 9 12 unit condition pf v,,=o.ov pf vnr ,t=o.ov rev. 1.9 sharp .- lhflgka7 . - 33 2.2 ac input/output test conditions yg-j(iqzzq~z ac test inputs are driven at 2.7v for a logic ?1? and o.ov for a logic ?0.? input timing begins, and output timing ends, at 1.35v. input rise and fall times (10% to 90%) ~10 ns. figure 14. transient input/output reference waveform for vc,=2.7v-3.6v 4 ~~~~z2~~pg- ac test inputs are driven at 3.ov for a logic ?1? and o.ov for a logic ?0.? input timing begins, and output timing ends, at 1 sv. input rise and fail times (10% to 90%) cl 0 ns. figure 15. transient input/output reference waveform for vcc=3.3v*o.3v 1.3v f ln914 cl includes jig a cl capacitance t - figure 16. transient equivalent testing load circuit test configuration capacitance loading value test configuration cjpf) =3.3v~0.3v, 2.7v-3.6v 1 50 rev. 1.9 sharp lhf16ka7 . - 34 . a 6.2.3 dc characteristics dc characteristics v,c=2.n vcc=3.3v test sym. parameter notes typ. max. typ. max. unit conditions ?ll input load current 1 *0.5 io.5 pa vcc=v,,max. vin=vcc or gnd ?lo output leakage current 1 5zo.5 rto.5 pa ;~?3?????? =vct: or gnd ?cc, vcc standby current 1,396 cmos inputs 20 100 20 100 pa v,,=v,,max. ce#=rp#=vccf0.2v ttl inputs 1 4 1 4 ma vcc=vccmax. ce#=rp#=v,, lccd i v,, deep power-down 1 , 20 20 ha rp#=gndi0.2v current &-,,,(sts)=oma ?cm v,, read current 1,5,6 cmos inputs block erase full chi block erase full chi rev. 1.9 lhflgka7 -- - dc characteristics (continued) v,,=2.n? v&.3v test sym. parameter notes min. max. min. max. unit conditions v,, input low voltage 7 -0.5 0.8 -0.5 0.8 v hi input high voltage 7 2.0 kc 2.0 +0.5 vcc v +0.5 bl output low voltage voh, output high voltage vw voh2 output high voltage (cmos) v,,,, v,, lockout voltage during normal operations v,,,, ?v,, voltage during write or erase operations v,,,, v,, voltage during write or erase operations vpphs v,, voltage during write or erase operations v, kn vcc lockout voltage notes: 4,7 1.5 1.5 v 2.7 3.6 - - v 3.0 3.6 3.0 3.6 v 4.5 5.5 4.5 5.5 v 2.0 2.0 v 1. all currents are in rms unless otherwise noted. typical values at nominal vcc voltage and ta=+25?c. 2* icc,, and bces are specified with the device de-selected. if read or byte written while in erase suspend mode, the device?s current draw is the sum of i,,,, or icces and lccr or iccw, respectively. 3. includes sts. 4. block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when v,+v,,,k, and not guaranteed in the range between v,,lk(max.) and v,,,, (min.), between v,,,, (max.) and vpphp(min.), between vpp,+(max.) and vpphs(min.) and above vpphs(max.). 5. automatic power savings (aps) reduces typical iccn to 3ma at 2.7v and 3.3v vcc in static operation. 6. cmos inputs are either vcc*o.2v or gndko.2v. ttl inputs are either v,, or v,,. 7. sampled, net 100% tested. ? i rev. 1.9 sharp lhf16ka7 36 _ - -- - 6.2.4 ac characteristics - read-only operations(?) sym. i t . .._.. vcc=2.7v-3.6v, t,=40?c to +85x versiond4) 1 lh28f160s3h-l120 parameter 1 notes 1 min. 1 max. unit byte# to output delay 3 120 ns ~~~~~ byte# to output in high 2 3 30 ns telfl ff, fh ce# low to byte# high or low 3 5 ns note: see 3.3v vcc read-only operations for notes 1 through 4. i v ,&3.3ko.3\ i, tp40?c to +85x ii sym. i versians(4) _ -_-_-.-- parameter 1 lh28f160s3h-ll oo ( notes i min. i max. unit i i tavnv 1 read cycle time 100 ns ii tavnv address to output delay 100 ns ff, 0? ce# to output delay 2 100 ns h rp# high to - . . - ? uutput ueray i i i aa_ tluu i ns ,. .& n-l... , r) ac nv oe# to output welay -vi) ns in low 2 -; 0 ns high z 3 50 ns ff, (jy ce# to output _fetic;v ce# high to output in oe# to output in low z ? l?y 3 0 ns 20 ns bh output hold from address, ce# or oe# change, whichever occurs first 3 0 ns flqv byte# to output delay 3 100 ns fhnv tj, n, byte# to output in high z 3 30 ns flfl ce# low to byte/# high or low 3 5 ns fi fh notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to telqv-&ai, after the falling edge of ce# without impact on 3. sampled, not 100% tested. 4. see ordering information for device speeds (valid operational combinations). rev. 1.9 sharp r device address selection address stable data valid 1.11.11111 tavav vih ce#(e) vil vih oe#(g) vil ,.,o....mn voh vol 4 tavqv b kc ?????- note: ce# i&defined as the latter of cl&# and ce# going low or the first of ceo# or ce$ going high. - lhf16ka7 37 _ - . i - figure 17. ac waveform for read operations rev. 1.9 sharp lhflgka7 device address selection data valid 1..1.11..1 address stable vih k cwe) vil tavfl=telfl vih oe#(g) vil qjih byte#(f) vil voh voh note: ce# is defined as the latter of ceo# and cei# going low or the first of ceo# or ce+# going high. figure 18. byte# timing waveforms rev. 1.9 sharp lhflgka7 39 6.2.5 ac characteristics - write operations(?) note: see 3.3v vcc we#-controlled writes for notes 1 through 5. sym. i vcc:=3.3v+0.3v, t,=40?c to +85?c versions@) 1 lh28f160s3h-ll oo parameter 1 notes ) min. ) max. unit twclr,, write recovery before read 0 ns vpp hold from valid srd, sts high z 2,4 0 ns wp# vi,, hold from valid srd, sts high z z4 0 ns notes: 1. read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 4 for valid a,,,, and d,, for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. vpp should be held at v,ph1,2j3 until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (sr.1/3/4/5=0). 5. see ordering information for device speeds (valid operational combinations). rev. 1.9 shari= lhflgka7 addresses(a) notes: 1. vcc power-up and standby. 2. write erase or write setup. 3. write erase confirm orvalid address and data. 4. automated erase or program delay. 5. read stat®ister data. 1 6. write read array command. 7. ce# is defined as the latter of ceo# and ce,# going low or the first of ceo# or ce,# going high. figure 19. ac waveform for we#-controlled write operations rev. 1.9 sharp lhf16ka7 -- - 6.2.6 alternative ce#-controlled writes(?) i v ,,=2.7\1-3.6\ ~-40c to +85?c 1 lh28f160s3h-l120 1 i ( notes 1 min. ( max. unit ! sym. 1 versions@) parameter om ce# hiah h we# hold fr tfwf, 8 ce# pulse widt ..- :h high 25 ns tfq+n, ce# high to sts going low 100 ns ffhg, write recovery before read 0 ns vpp hold from valid srd, sts high z 24 0 ns wp# vih hold from valid srd, sts high z 2,4 0 ns note: see 3.3v vco alternative ce#-controlled writes for nc )tes 1 through 5. ( write cycle time i 100 i clfl 1 rp# high recovery to ce# going low 2 1 11 tfwax i address hold from ce# high t?pfw vpp setup to ce# goi tjjfh address setup to ce# going high 3 50 $-)?fh datd setup to ce# going high write recovery before read tfclr,, hwl vpp hold from valid srd, sts high z tnvsl wp# v,, , hold from valid srd, sts high z notes: 0 ns 24 0 ns 2,4 0 ns 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid a,, and d,, for block erase, full chip erase, (multi) word/byte write or block lock-bit configuration. 4. v,, should be held at v,,,,,z,, until determination of block erase, full chip erase, (multi) word/byte write or block lock-bit configuration success (sr.1/3/4/5=0). 5. see ordering information for device speeds (valid operational combinations). rev. 1.9 shari= addresses(a) we#(w) oe#(g) ce#(e) data(d/q) sts(r) lhflgka7 1 2 3 4 a- 6 a--- vih notes: 1. vcc power-up and standby. 2. write erase or write setup. 3. write erase confirm orvalid address and data. 4. automated erase or program delay. 5. read status?register data. 6. write read array command. 7. ce# is defined as the latter of ceo# and ce,# going low or the first of ce& or ce+ going high. figure 20. ac waveform for ce#-controlled write operations rev. 1.9 shari= lhflgka7 l . . ; reset operations high z sts(r) vol vih rp#(p) vil tplph (a)reset during read array mode high z sts( r) vol vih rp#(p) 4 ml (b)reset during block erase, full chip erase, (multi) word/byte write or block lock-bit configuretion 2.7f3.3v vcc wl vih rp#( p) i vil i- (c)vcc power up timing figure 21. ac waveform for reset operation reset ac specifications v,.,=2.7v vr.c=3.3v symbol parameter rp#/ pulse low time notes min. max. min. max. unit tplph (if rp# is tied to vcc, this specification is 100 100 ns not applicable) tplrh rp# low to reset during block erase, full chip erase, (multi) word/byte write 1,2 21.5 21.1 ijs or block lock-bit configuration t23vph vcc at 2.7v to rp# high vcn at 3.ov to rp# high 3 - 100 100 ns motes: 1. if rp# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration operation is not executing, the reset will complete within 1 oons. 3. a reset time, tphov, is required from the latter of sts going high z or rp# going high until outputs are valid. 3. when the device power-up, holding rp# low minimum 1oons is required after vcc has been in predefined range and also has been in stable there. rev. 1.9 sharp lhflgka7 44 -- - 6.2.8 block erase, full chip erase, (multi) word/byte write and block lock-bit configuration performance@) vnn=2.7v-3.6v, ta=-40?c to +85?c vp,=2.7v-3.6v vp,=3.0v-3.6v vp,=4.5v-ssv sym. parameter notes ? typ.(l) max. typ.(?) max. typ.(?) max. unit twhqvl word/byte write time (using write, w/b in word 2 22.19 250 22.19 250 13.2 180 tehqv1 ps mode) twhqyl word/byte write time 250 19.9 250 13.2 180 tehqvl (using write, byte w/b in 2 19.9 us mode) word/byte write time (using multi word/byte write) 2 5.76 250 5.76 250 2.76 180 vs block write time (using w/b write, in word 2 0.73 8.2 0.73 8.2 0.44 4.8 s 4 mode) block write time , note: see 3.3v v&block erase, full chirj erase, (multi) word/byte write and block lock-bit configuration performance for notes 1 through 3. rev. 1.9 shal?i= lhflgka7 _ - -- voc=3.3v+0.3v, t,,=-40c to +85?c vp,=3.0v-3.6v vpp=4.5v-5.5v sym. parameter notes typ.(?) 1 max. typ.(?) 1 max. unit tw,,ov, word/byte write time i i (using w/b write, in word mode) 2 21.75 250 12.95 180 tf,,,,,,, ijs phqvl word/byte write time fwr,v, (using w/b write, in byte mode) 2 19.51 250 12.95 180 ijs word/byte write time (using multi word/byte write) 2 5.66 250 2.7 180 p ii , block write time i r) i nvr, i a.2 1 0.43 1 4.8 1 s 1 ii (using w/b write, in word mode) i block write time i q i 4 r)n i i5.5 l , i .l? 1 0.85 1 10.9 1 s /i ii (using w/b write, in byte mode) ii i block write time (using multi word/byte write) i ?.j? -r f block erase time 2 0.55 10 0.41 10 s fhnv7 \ full chip erase time 17.6 320 13.1 320 s ?whqvs set block lock-bit time 2 21.75 250 12.95 180 bg ijs iwhqv4 clear block lock-bits time 2 0.55 10 0.41 10 s fhova :whnht write suspend latency time to read 7.1 10 6.6 9.3 ljs fhrhi phnh2 erase suspend latency time to read 15.2 21 .l 12.3 17.2 ijs fhrh7 notes: 1. typical values measured at ta=+25?c and nominal voltages. assumes corresponding block lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. sampled but not 100% tested. rev. 1.9 sharp lhflgka7 46 _ - . . l 7 additional information 7.1 ordering information product line designator for all sharp flash products i i i [l/h12/8)fil~6~01s13~h~t~-1l~l~o~al i i device density 160 = 16-mbit architecture s = regular block 4 power supply type 3 = smart 3 technology j acts speed (ns) 1o:l oons (3.3v), 120ns (2.7v) 13:130ns (3.3v), 150ns (2.7v) operating temperature] blank = 0c - +7o?c h = -40c - +85?c package t = 56-lead tsop r = 56-lead tsop(reverse bend) ns = 56-lead ssop b = 64-ball csp d = 64-lead sdip valid operational combinations v,,=2.7v-3.6v v(--=3.3v+o.3v 5opf load, 5opf load, option order code 1.35v i/o levels 1 sv l/o levels 1 lh28f160s3ht-ll oa lh28f160s3h-l120 lh28f160s3h-ll oo .i? rev. 1.9 sharp lhf16ka7 47 flash memory lhfxkxx family data protection noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto we# signal or power supply, may be interpreted as false commands, causing undesired memory updating. to protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) protecting data in specific block setting the lock bit of the desired block and pulling wp# low disables the writing operation on that block. by using this feature, the flash memory space can be divided into, for example, the program section(locked section) and data section(unlocked set t ion). by controlling wp#, desired blocks can be locked/unlocked through the software. for further information on setting/resetting block bit, refer to the specification. (see chapter 4.12 and 4.13.) 2) data protection through vpp when the level of vpp is lower than vpplk (lockout voltage), write operation on the flashmemory is disabled. all blocks are lockedandthedata intheblocksarecompletely write protected. ..? for the l&kout voltage, refer to the specification. (see chapter 6.2.3. > 3) data protection through rp# when the rp# is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. for the detai 1s of rp# control, refer to the specification. (see chapter 5.6 and 6.27. ) rev 1.9 sharp ~. lhf16ka7 48 _ - -- - lh28f16osxx-lxx flash memory errata 1. multi word/byte write operations . probj,emt when two planes of 32-byte page buffer are both in full and first buffer data are being written to the flash array, the extended status register bit xsr.7 may be erroneously set to ?l?, which indicates the multi word/byte write command is available. workaround (1) usk one page buffer after writing the data by the multi word/byte write command, the status register must be read to check the bit sr.7. at this point, the device is in read status register mode whether the read status register command is written or not. after the status register bit sr.7 is set to ?l?, the next multi word/byte write command will be available. (2) use two page buffers after writing the data in two planes by the multi word/byte write command, the status register must be read to check the bit sr.7. at this point, the device is in read status register mode whether the read status register command is written or not. after the status register bit sr.7 is set to ?1?) the next multi word/byte write command will be available. .,l? sharp lhf16ka7 49 _ - -- - lh28f160sxx-lxx flash memory errata use one page buffer start r.. ____ _ _ __ _ ___ _ __ ___ _ _ _ . _ ___ __ __ _ _ ___ __ __ __. . . . ._ . . . . . . . - ~~-~~--~~~: command sequence 1 write e8h 1 read xsr start address sharp related document information(?) document no. document name ap-ooi-sd-e flash memory family so&are drivers ap-oodft-e data protection method of sharp flash memory ap-o07-s w-e note : r.p#, vpp ekctfic potentiai switching circuit i. inmational customers should contact their local sharp or distribution sales office. sharp preliminary 3l is j i ase plane g detail a $6 i !i - ftt-az ; tin-u i* 1%flshlr?f%t& d9 5sttrrwf3. j(e i tsop56-p-1420 lead finish ! plating note plastic body dimensions do not include burr of resin. ra?iiing no. ! aa1115 4a i unit i mm |
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